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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8571/ad8572/AD8574 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 zero-drift, single-supply, rail-to-rail input/output operational amplifiers 8-lead soic (r suffix) 1 2 3 4 8 7 6 5 ad8571 2 in a v 2 +in a v+ out a nc nc nc nc = no connect 1 2 3 4 8 7 6 5 ad8572 2 in a v 2 +in a out b 2 in b v+ +in b out a 14-lead soic (r suffix) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 2 in a +in a v+ +in b 2 in b out b out d 2 in d +in d v 2 +in c 2 in c out c out a AD8574 features low offset voltage: 1 m v input offset drift: 0.005 m v/ 8 c rail-to-rail input and output swing 5 v/2.7 v single-supply operation high gain, cmrr, psrr: 130 db ultralow input bias current: 20 pa low supply current: 750 m a/op amp overload recovery time: 50 m s no external capacitors required applications temperature sensors pressure sensors precision current sensing strain gage amplifiers medical instrumentation thermocouple amplifiers general description this new family of amplifiers has ultralow offset, drift and bias current. the ad8571, ad8572 and AD8574 are single, dual and quad amplifiers featuring rail-to-rail input and output swings. all are guaranteed to operate from 2.7 v to 5 v single supply. the ad857x family provides the benefits previously found only in expensive autozeroing or chopper-stabilized amplifiers. using analog devices new topology these new zero-drift amplifiers combine low cost with high accuracy. (no external capacitors are required.) in addition, using a patented spread-spectrum autozero technique, the ad857x family virtually eliminates the intermodulation effects from interaction of the chopping function with the signal frequency in ac applications. with an offset voltage of only 1 m v and drift of 0.005 m v/ c, the ad8571 is perfectly suited for applications where error sources cannot be tolerated. position, and pressure sensors, medical equipment, and strain gage amplifiers benefit greatly from nearly zero drift over their operating temperature range. many more systems require the rail-to-rail input and output swings provided by the ad857x family. the ad857x family is specified for the extended industrial/automotive (C40 c to +125 c) temperature range. the ad8571 single is available in 8-lead msop and narrow 8-lead soic packages. the ad8572 dual amplifier is available in 8-lead narrow so and 8-lead tssop surface mount packages. the AD8574 quad is available in narrow 14-lead soic and 14-lead tssop packages. 8-lead msop (rm suffix) 2 in a 1 in a v 2 v+ out a nc 1 45 8 ad8571 nc nc = no connect nc 8-lead tssop (ru suffix) 2 in a +in a v 2 out b 2 in b +in b v+ 1 4 5 8 ad8572 out a 14-lead tssop (ru suffix) out a 2 in a 1 in a v 1 2 in d 1 in d v 2 out d 1 n b 2 in b out b 2 in c out c 1 in c AD8574 1 14 78 pin configurations 8-lead soic (r suffix)
C2C rev. 0 ad8571/ad8572/AD8574Cspecifications electrical characteristics parameter symbol conditions min typ max unit input characteristics offset voltage v os 15 m v C40 c t a +125 c10 m v input bias current i b 10 50 pa C40 c t a +125 c 1.0 1.5 na input offset current i os 20 70 pa C40 c t a +125 c 150 200 pa input voltage range 05v common-mode rejection ratio cmrr v cm = 0 v to 5 v 120 140 db C40 c t a +125 c 115 130 db large signal voltage gain 1 a vo r l = 10 k w , v o = 0.3 v to 4.7 v 125 145 db C40 c t a +125 c 120 135 db offset voltage drift d v os / d t C40 c t a +125 c 0.005 0.04 m v/ c output characteristics output voltage high v oh r l = 100 k w to gnd 4.99 4.998 v C40 c to +125 c 4.99 4.997 v r l = 10 k w to gnd 4.95 4.98 v C40 c to +125 c 4.95 4.975 v output voltage low v ol r l = 100 k w to v+ 1 10 mv C40 c to +125 c210mv r l = 10 k w to v+ 10 30 mv C40 c to +125 c1530mv short circuit limit i sc 25 50 ma C40 c to +125 c 40 ma output current i o 30 ma C40 c to +125 c 15 ma power supply power supply rejection ratio psrr v s = 2.7 v to 5.5 v 120 130 db C40 c t a +125 c 115 130 db supply current/amplifier i sy v o = 0 v 850 975 m a C40 c t a +125 c 1,000 1,075 m a dynamic performance slew rate sr r l = 10 k w 0.4 v/ m s overload recovery time 0.05 0.3 ms gain bandwidth product gbp 1.5 mhz noise performance voltage noise e n pCp 0 hz to 10 hz 1.3 m v pCp e n pCp 0 hz to 1 hz 0.41 m v pCp voltage noise density e n f = 1 khz 51 nv/ ? hz current noise density i n f = 10 hz 2 fa/ ? hz note 1 gain testing is highly dependent upon test bandwidth. specifications subject to change without notice. (v s = 5 v, v cm = 2.5 v, v o = 2.5 v, t a = 25 8 c unless otherwise noted)
C3C rev. 0 ad8571/ad8572/AD8574 electrical characteristics parameter symbol conditions min typ max unit input characteristics offset voltage v os 15 m v C40 c t a +125 c10 m v input bias current i b 10 50 pa C40 c t a +125 c 1.0 1.5 na input offset current i os 10 50 pa C40 c t a +125 c 150 200 pa input voltage range 0 2.7 v common-mode rejection ratio cmrr v cm = 0 v to 2.7 v 115 130 db C40 c t a +125 c 110 130 db large signal voltage gain 1 a vo r l = 10 k w , v o = 0.3 v to 2.4 v 110 140 db C40 c t a +125 c 105 130 db offset voltage drift d v os / d t C40 c t a +125 c 0.005 0.04 m v/ c output characteristics output voltage high v oh r l = 100 k w to gnd 2.685 2.697 v C40 c to +125 c 2.685 2.696 v r l = 10 k w to gnd 2.67 2.68 v C40 c to +125 c 2.67 2.675 v output voltage low v ol r l = 100 k w to v+ 1 10 mv C40 c to +125 c210mv r l = 10 k w to v+ 10 20 mv C40 c to +125 c1520mv short circuit limit i sc 10 15 ma C40 c to +125 c 10 ma output current i o 10 ma C40 c to +125 c 5ma power supply power supply rejection ratio psrr v s = 2.7 v to 5.5 v 120 130 db C40 c t a +125 c 115 130 db supply current/amplifier i sy v o = 0 v 750 900 m a C40 c t a +125 c 950 1,000 m a dynamic performance slew rate sr r l = 10 k w 0.5 v/ m s overload recovery time 0.05 ms gain bandwidth product gbp 1 mhz noise performance voltage noise e n pCp 0 hz to 10 hz 2.0 m v pCp voltage noise density e n f = 1 khz 94 nv/ ? hz current noise density i n f = 10 hz 2 fa/ ? hz note 1 gain testing is highly dependent upon test bandwidth. specifications subject to change without notice. (v s = 2.7 v, v cm = 1.35 v, v o = 1.35 v, t a = 25 8 c unless otherwise noted)
ad8571/ad8572/AD8574 C4C rev. 0 absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v input voltage . . . . . . . . . . . . . . . . . . . . . . gnd to v s + 0.3 v differential input voltage 2 . . . . . . . . . . . . . . . . . . . . . . 5.0 v esd (human body model) . . . . . . . . . . . . . . . . . . . . . 2,000 v output short-circuit duration to gnd . . . . . . . . . indefinite storage temperature range rm, ru and r packages . . . . . . . . . . . . . C65 c to +150 c operating temperature range ad8571a/ad8572a/AD8574a . . . . . . . . C40 c to +125 c junction temperature range rm, ru and r packages . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 differential input voltage is limited to 5.0 v or the supply voltage, whichever is less. package type u ja 1 u jc unit 8-lead msop (rm) 190 44 c/w 8-lead tssop (ru) 240 43 c/w 8-lead soic (r) 158 43 c/w 14-lead tssop (ru) 180 36 c/w 14-lead soic (r) 120 36 c/w note 1 q ja is specified for worst-case conditions, i.e., q ja is specified for device in socket for p-dip packages, q ja is specified for device soldered in circuit board for soic and tssop packages. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8571/ad8572/AD8574 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide temperature package package model range description option brand 1 ad8571arm 2 C40 c to +125 c 8-lead msop rm-8 aja ad8571ar C40 c to +125 c 8-lead soic so-8 ad8572aru 3 C40 c to +125 c 8-lead tssop ru-8 ad8572ar C40 c to +125 c 8-lead soic so-8 AD8574aru 3 C40 c to +125 c 14-lead tssop ru-14 AD8574ar C40 c to +125 c 14-lead soic so-14 notes 1 due to package size limitations, these characters represent the part number. 2 available in reels only. 1,000 or 2,500 pieces per reel. 3 available in reels only. 2,500 pieces per reel.
ad8571/ad8572/AD8574 C5C rev. 0 offset voltage C m v number of amplifiers 180 0 2 2.5 0.5 120 100 60 20 2.5 v s = 2.7v v cm = 1.35v t a = 25 8 c 40 80 140 160 2 1.5 2 0.5 1.5 figure 1. input offset voltage distribution at 2.7 v offset voltage C m v number of amplifiers 180 0 120 100 60 20 v s = 5v v cm = 2.5v t a = 25 8 c 40 80 140 160 2 2.5 0.5 2.5 2 1.5 2 0.5 1.5 figure 4. input offset voltage distribution at 5 v load current C ma 10 0.1 0.001 output voltage C mv 0.1 110 1 100 10k source sink v s = 2.7v t a = 25 8 c 100 1k 0.0001 0.01 figure 7. output voltage to supply rail vs. output current at 2.7 v inp u t co mm o n-m o de v o lta g e C v input bias current C pa 50 2 30 01 5 234 40 30 20 2 10 2 20 10 0 v s = 5v t a = 2 40 8 c, +25 8 c, +85 8 c 2 40 8 c +25 8 c +85 8 c figure 2. input bias current vs. common-mode voltage input offset drift C nv/ 8 c number of amplifiers 12 0 01 6 23 4 5 10 8 4 2 6 v s = 5v v cm = 2.5v t a = 2 40 8 c to +125 8 c figure 5. input offset voltage drift distribution at 5 v temperature C 8 c input bias current C pa 1,000 0 2 75 2 50 125 2 25 0 25 50 75 100 750 500 250 150 v cm = 2.5v v s = 5v figure 8. bias current vs. temperature common-mode voltage C v input bias current C pa 1,500 2 2,000 01 5 234 1,000 500 0 2 1,000 2 1,500 2 500 v s = 5v t a = 125 8 c figure 3. input bias current vs. common-mode voltage load current C ma 10 0.1 0.001 output voltage C mv 0.1 110 1 100 10k source sink v s = 5v t a = 25 8 c 100 1k 0.0001 0.01 figure 6. output voltage to supply rail vs. output current at 5 v temperature C 8 c supply current C ma 1.0 0.8 0 2 75 2 50 125 2 25 0 25 50 75 100 0.6 0.4 0.2 150 5v 2.7v figure 9. supply current vs. temperature typical performance characteristicsC
ad8571/ad8572/AD8574 C6C rev. 0 supply voltage C v supply current per amplifier C m a 800 0 700 400 300 200 100 600 500 0 16 2345 t a = 25 8 c figure 10. supply current vs. supply voltage frequency C hz closed-loop gain C db 100 1k 10m 10k 100k 1m 60 50 2 40 40 30 20 10 0 2 10 2 20 2 30 a v = 2 100 v s = 2.7v c l = 0pf r l = 2k v a v = 2 10 a v = +1 figure 13. closed loop gain vs. frequency at 2.7 v frequency C hz output impedance C v 100 1k 10m 10k 100k 1m 300 270 0 240 210 180 150 120 90 60 30 v s = 5v a v = 100 a v = 1 a v = 10 figure 16. output impedance vs. frequency at 5 v frequency C hz open-loop gain C db 10k 100k 100m 1m 10m 60 50 2 40 40 30 20 10 0 2 10 2 20 2 30 45 90 135 180 225 270 0 phase shift C de g rees v s = 2.7v c l = 0pf r l = figure 11. open-loop gain and phase shift vs. frequency at 2.7 v a v = 2 100 frequency C hz closed-loop gain C db 100 1k 10m 10k 100k 1m 60 50 2 40 40 30 20 10 0 2 10 2 20 2 30 v s = 5v c l = 0pf r l = 2k v a v = 2 10 a v = +1 figure 14. closed loop gain vs. frequency at 5 v 2 m s 500mv v s = 2.7v c l = 300pf r l = 2k v a v = 1 figure 17. large signal transient response at 2.7 v frequency C hz open-loop gain C db 10k 100k 100m 1m 10m 60 50 2 40 40 30 20 10 0 2 10 2 20 2 30 45 90 135 180 225 270 0 phase shift C de g rees v s = 5v c l = 0pf r l = figure 12. open-loop gain and phase shift vs. frequency at 5 v frequency C hz output impedance C v 100 1k 10m 10k 100k 1m 300 270 0 240 210 180 150 120 90 60 30 v s = 2.7v a v = 100 a v = 1 a v = 10 figure 15. output impedance vs. frequency at 2.7 v 5 m s 1v v s = +5v c l = 300pf r l = 2k v a v = 1 figure 18. large signal transient response at 5 v
ad8571/ad8572/AD8574 C7C rev. 0 5 m s 50mv v s = 6 1.35v c l = 50pf r l = a v = 1 figure 19. small signal transient response at 2.7 v capacitance C p f small signal overshoot C % 10 100 10k 1k 45 0 40 35 30 25 20 15 10 5 +os 2 os v s = 6 2.5v r l = 2k v t a = 25 8 c figure 22. small signal overshoot vs. load capacitance at 5 v 200 m s 1v v s = 6 2.5v r l = 2k v a v = 2 100 v in = 60mv p-p figure 25. no phase reversal 5 m s 50mv v s = 6 2.5v c l = 50pf r l = a v = 1 figure 20. small signal transient response at 5 v v s = 6 2.5v v in = 2 200mv p-p (ret to gnd) c l = 0pf r l = 10k v a v = 2 100 20 m s 1v 0v v in v out 0v bottom scale: 1v/div top scale: 200mv/div figure 23. positive overvoltage recovery frequency C hz cmrr C db 140 80 0 100 1k 10m 10k 100k 1m 60 120 20 40 100 v s = 2.7v figure 26. cmrr vs. frequency at 2.7 v capacitance C pf small signal overshoot C % 10 100 10k 1k 50 45 0 40 35 30 25 20 15 10 5 +os 2 os v s = 6 1.35v r l = 2k v t a = 25 8 c figure 21. small signal overshoot vs. load capacitance at 2.7 v v s = 6 2.5v v in = 200mv p-p (ret to gnd) c l = 0pf r l = 10k v a v = 2 100 20 m s 1v v in 0v 0v v out bottom scale: 1v/div top scale: 200mv/div figure 24. negative overvoltage recovery frequency C hz cmrr C db 140 80 0 100 1k 10m 10k 100k 1m 60 120 20 40 100 v s = 5v figure 27. cmrr vs. frequency at 5 v
ad8571/ad8572/AD8574 C8C rev. 0 frequency C hz psrr C db 140 80 0 100 1k 10m 10k 100k 1m 60 120 20 40 100 +psrr 2 psrr v s = 6 1.35v figure 28. psrr vs. frequency at 1.35 v frequency C hz output swing C v p-p 3.0 2.5 0 100 1k 1m 10k 100k 2.0 1.5 0.5 1.0 3.5 4.0 4.5 5.0 5.5 v s = 6 2.5v r l = 2k v a v = 1 thd+n < 1% t a = 25 8 c figure 31. maximum output swing vs. frequency at 5 v e n C nv/ hz v s = 2.7v r s = 0 v 0.5 frequency C khz 1.0 1.5 2.0 2.5 0 104 156 208 260 312 364 52 figure 34. voltage noise density at 2.7 v from 0 hz to 2.5 khz frequency C hz psrr C db 140 80 0 100 1k 10m 10k 100k 1m 60 120 20 40 100 +psrr 2 psrr v s = 6 2.5v figure 29. psrr vs. frequency at 2.5 v 1s 50mv v s = 6 1.35v a v = 120,000 0v figure 32. 0.1 hz to 10 hz noise at 2.7 v e n C nv/ hz v s = 2.7v r s = 0 v 5 frequency C khz 10 15 20 25 0 32 48 64 80 96 112 16 figure 35. voltage noise density at 2.7 v from 0 hz to 25 khz frequency C hz output swing C v p-p 3.0 2.5 0 100 1k 1m 10k 100k 2.0 1.5 0.5 1.0 v s = 6 1.35v r l = 2k v a v = 1 thd+n < 1% t a = 25 8 c figure 30. maximum output swing vs. frequency at 2.7 v 1s 50mv v s = 6 2.5v a v = 120,000 figure 33. 0.1 hz to 10 hz noise at 5 v v s = 5v r s = 0 v 0.5 frequency C khz 1.0 1.5 2.0 2.5 0 52 78 104 130 156 182 26 e n C nv/ hz figure 36. voltage noise density at 5 v from 0 hz to 2.5 khz
ad8571/ad8572/AD8574 C9C rev. 0 e n C nv/ hz 510152025 0 v s = 5v r s = 0 v frequency C khz 32 48 64 80 96 112 16 figure 37. voltage noise density at 5 v from 0 hz to 25 khz 2 10 temperature C 8 c short-circuit current C ma 50 30 2 50 2 75 2 50 125 2 25 0 25 50 75 100 10 150 v s = 2.7v 2 40 2 30 2 20 0 20 40 i sc 2 i sc+ figure 40. output short-circuit current vs. temperature 100 temperature C 8 c output voltage swing C mv 250 200 0 2 75 2 50 125 2 25 0 25 50 75 100 150 150 v s = 5v 25 50 75 125 175 225 r l = 1k v r l = 10k v r l = 100k v figure 43. output voltage to supply rail vs. temperature e n C nv/ hz v s = 5v r s = 0 v 510 0 frequency C hz 60 90 120 150 180 210 30 figure 38. voltage noise density at 5 v from 0 hz to 10 hz 2 20 temperature C 8 c short-circuit current C ma 100 60 2 100 2 75 2 50 125 2 25 0 25 50 75 100 20 150 v s = 5v 2 80 2 60 2 40 0 40 80 i sc 2 i sc+ figure 41. output short-circuit current vs. temperature temperature C 8 c power supply rejection C db 150 145 125 2 75 2 50 125 2 25 0 25 50 75 100 140 135 130 150 v s = 2.7v to 5.5v figure 39. power-supply rejection vs. temperature 100 temperature C 8 c output voltage swing C mv 250 200 0 2 75 2 50 125 2 25 0 25 50 75 100 150 150 v s = 5v 25 50 75 125 175 225 r l = 1k v r l = 10k v r l = 100k v figure 42. output voltage to supply rail vs. temperature
ad8571/ad8572/AD8574 C10C rev. 0 functional description the ad857x family are cmos amplifiers that achieve their high degree of precision through random frequency autozero stabilization. the autocorrection topology allows the ad857x to maintain its low offset voltage over a wide temperature range, and the randomized autozero clock eliminates any intermodulation distortion (imd) errors at the amplifiers output. the ad857x can be run from a single supply voltage as low as 2.7 v. the extremely low offset voltage of 1 m v and no imd products allows the amplifier to be easily configured for high gains without risk of excessive output voltage errors. this makes the ad857x an ideal amplifier for applications requiring both dc precision and low distortion for ac signals. the extremely small temperature drift of 5 nv/ c ensures a minimum of offset voltage error over its entire temperature range of C40 c to +125 c. these combined features make the ad857x an excellent choice for a variety of sensitive measurement and automotive applications. amplifier architecture each ad857x op amp consists of two amplifiers, a main amplifier and a secondary amplifier, used to correct the offset voltage of the main amplifier. both consist of a rail-to-rail input stage, allowing the input common-mode voltage range to reach both supply rails. the input stage consists of an nmos differential pair operating concurrently with a parallel pmos differential pair. the outputs from the differential input stages are combined in another gain stage whose output is used to drive a rail-to-rail output stage. the wide voltage swing of the amplifier is achieved by using two output transistors in a common-source configuration. the output voltage range is limited by the drain-to-source resistance of these transistors. as the amplifier is required to source or sink more output current, the voltage drop across these transistors increases due to their rds. simply put, the output voltage will not swing as close to the rail under heavy output current conditions as it will with light output current. this is a characteristic of all rail-to-rail output amplifiers. figures 6 and 7 show how close the output voltage can get to the rails with a given output current. the out- put of the ad857x is short circuit protected to approximately 50 ma of current. the ad857x amplifiers have exceptional gain, yielding greater than 120 db of open-loop gain with a load of 2 k w . because the output transistors are configured in a common-source configu- ration, the gain of the output stage, and thus the open-loop gain of the amplifier, is dependent on the load resistance. open-loop gain will decrease with smaller load resistances. this is another characteristic of rail-to-rail output amplifiers. basic autozero amplifier theory autocorrection amplifiers are not a new technology. various ic implementations have been available for over 15 years and some improvements have been made over time. the ad857x design offers a number of significant performance improvements over older versions while attaining a very substantial reduction in device cost. this section offers a simplified explanation of how the ad857x is able to offer extremely low offset voltages and high open-loop gains. as noted in the previous section on amplifier architecture, each ad857x op amp contains two internal amplifiers. one is used as the primary amplifier, the other as an autocorrection, or nulling, amplifier. each amplifier has an associated input offset voltage that can be modeled as a dc voltage source in series with the noninverting input. in figures 44 and 45 these are labeled as v osx , where x denotes the amplifier associated with the offset; a for the nulling amplifier, b for the primary amplifier. the open- loop gain for the +in and Cin inputs of each amplifier is given as a x . both amplifiers also have a third voltage input with an associated open-loop gain of b x . there are two modes of operation determined by the action of two sets of switches in the amplifier: an autozero phase and an amplification phase. autozero phase in this phase, all f a switches are closed and all f b switches are opened. here, the nulling amplifier is taken out of the gain loop by shorting its two inputs together. of course, there is a degree of offset voltage, shown as v osa , inherent in the nulling amplifier, which maintains a potential difference between the +in and Cin inputs. the nulling amplifier feedback loop is closed through f a 2 and v osa appears at the output of the nulling amp and on c m1 , an internal capacitor in the ad857x. mathematically, we can express this in the time domain as: vt av tbvt oa a osa a oa [] = [] - [] (1) which can be expressed as, vt av t b oa a osa a [] = [] + 1 (2) this shows us that the offset voltage of the nulling amplifier times a gain factor appears at the output of the nulling amplifier and thus on the c m1 capacitor. v in+ v in 2 v out a b a a f a f b v osa + b b c m2 c m1 f a f b v nb v na 2 b a v oa figure 44. autozero phase of the ad857x amplification phase when the f b switches close and the f a switches open for the amplification phase, this offset voltage remains on c m1 and essentially corrects any error from the nulling amplifier. the voltage across c m1 is designated as v na . let us also designate v in as the potential difference between the two inputs to the primary amplifier, or v in = (v in+ C v inC ). now the output of the nulling amplifier can be expressed as: vt avtv t bvt oa a in osa a na [] = [] - [] () - [] (3)
ad8571/ad8572/AD8574 C11C rev. 0 v in+ v in 2 v out a b a a f a f b v osa + b b c m2 c m1 f a f b v nb v na 2 b a v oa figure 45. output phase of the amplifier because f a is now open and there is no place for c m1 to dis- charge, the voltage v na at the present time t is equal to the voltage at the output of the nulling amp v oa at the time when f a was closed. if we call the period of the autocorrection switching frequency t s , then the amplifier switches between phases every 0.5 3 t s . therefore, in the amplification phase: vtv t t na na s [] =- ? ? 1 2 (4) and substituting equation 4 and equation 2 into equation 3 yields: vt avtav t abv t t b oa a in a osa a a osa s a [] = [] + [] - - ? ? + 1 2 1 (5) for the sake of simplification, let us assume that the autocorrection frequency is much faster than any potential change in v osa or v osb . this is a good assumption since changes in offset voltage are a function of temperature variation or long-term wear time, both of which are much slower than the auto-zero clock frequency of the ad857x. this effectively makes v os time invariant and we can rearrange equation 5 and rewrite it as: vt avt abv abv b oa a in a a osa a a osa a [] = [] + + () - + 1 1 (6) or, vt avt v b oa a in osa a [] = [] + + ? ? ? ? 1 (7) we can already get a feel for the autozeroing in action. note the v os term is reduced by a 1 + b a factor. this shows how the nulling amplifier has greatly reduced its own offset voltage error even before correcting the primary amplifier. now the primary amplifier output voltage is the voltage at the output of the ad857x amplifier. it is equal to: vtavtv bv out b in osb b nb [] = [] + () + (8) in the amplification phase, v oa = v nb , so this can be rewritten as: vtavtav bavt v b out b in b osb b a in osa a [] = [] ++ [] + + ? ? ? ? ? ? 1 (9) combining terms, vtvtaab abv b av out in b a b a b osa a b osb [] = [] + () + + + 1 (10) the ad857x architecture is optimized in such a way that a a = a b and b a = b b and b a >> 1. also, the gain product to a a b b is much greater than a b . these allow equation 10 to be simplified to: vtvtabav v out in a a a osa osb [] ? [] ++ () (11) most obvious is the gain product of both the primary and nulling amplifiers. this a a b a term is what gives the ad857x its extremely high open-loop gain. to understand how v osa and v osb relate to the overall effective input offset voltage of the complete amplifier, we should set up the generic amplifier equation of: vkvv out in os eff = + () , (12) where k is the open-loop gain of an amplifier and v os, eff is its effective offset voltage. putting equation 12 into the form of equation 11 gives us: vtvtabv ab out in a a os eff a a [] ? [] + , (13) and from here, it is easy to see that: v vv b os eff osa osb a , ? + (14) thus, the offset voltages of both the primary and nulling ampli- fiers are reduced by the gain factor b a . this takes a typical input offset voltage from several millivolts down to an effective input offset voltage of submicrovolts. this autocorrection scheme is what makes the ad857x family of amplifiers among the most precise amplifiers in the world. high gain, cmrr, psrr common-mode and power supply rejection are indications of the amount of offset voltage an amplifier has as a result of a change in its input common-mode or power supply voltages. as shown in the previous section, the autocorrection architecture of the ad857x allows it to quite effectively minimize offset voltages. the technique also corrects for offset errors caused by common-mode voltage swings and power supply variations. this results in superb cmrr and psrr figures in excess of 130 db. because the autocorrection occurs continuously, these figures can be maintained across the devices entire temperature range, from C40 c to +125 c. maximizing performance through proper layout to achieve the maximum performance of the extremely high input impedance and low offset voltage of the ad857x, care should be taken in the circuit board layout. the pc board sur- face must remain clean and free of moisture to avoid leakage currents between adjacent traces. surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. the use of guard rings around the amplifier inputs will further reduce leak- age currents. figure 46 shows how the guard ring should be configured and figure 47 shows the top view of how a surface mount layout can be arranged. the guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. by setting the guard ring voltage equal to the volt- age at the noninverting input, parasitic capacitance is minimized as well. for further reduction of leakage currents, components can be mounted to the pc board using teflon standoff insulators.
ad8571/ad8572/AD8574 C12C rev. 0 v out v in ad8572 v out v in ad8572 v out v in ad8572 figure 46. guard ring layout and connections to reduce pc board leakage currents v 2 v+ v ref v in1 v in2 guard ring r 2 r 2 r 1 r 1 ad8572 v ref guard ring figure 47. top view of ad8572 soic layout with guard rings other potential sources of offset error are thermoelectric voltages on the circuit board. this voltage, also called seebeck voltage, occurs at the junction of two dissimilar metals and is proportional to the temperature of the junction. the most common metallic junctions on a circuit board are solder-to-board trace and solder- to-component lead. figure 48 shows a cross-section diagram view of the thermal voltage error sources. if the temperature of the pc board at one end of the component (t a1 ) is different from the temperature at the other end (t a2 ), the seebeck voltages will not be equal, resulting in a thermal voltage error. this thermocouple error can be reduced by using dummy com- ponents to match the thermoelectric error source. placing the dummy component as close as possible to its partner will ensure both seebeck voltages are equal, thus canceling the thermo- couple error. maintaining a constant ambient temperature on the circuit board will further reduce this error. the use of a ground plane will help distribute heat throughout the board and will also reduce emi noise pickup. surface mount component component lead solder pc board copper trace v sc2 2 + + 2 v ts2 t a2 t a1 v sc1 2 + + 2 v ts1 if t a1 = t a2 , then v ts1 + v sc1 = v ts2 + v sc2 figure 48. mismatch in seebeck voltages causes a thermoelectric voltage error v out v in ad857x a v = 1 + (r f /r 1 ) r 1 r f r s = r 1 note: r s should be placed in close proximity and alignment to r 1 to balance seebeck voltages figure 49. using dummy components to cancel thermoelectric voltage errors 1/f noise characteristics another advantage of autozero amplifiers is their ability to cancel flicker noise. flicker noise, also known as 1/f noise, is noise inher- ent in the physics of semiconductor devices and increases 3 db for every octave decrease in frequency. the 1/f corner frequency of an amplifier is the frequency at which the flicker noise is equal to the broadband noise of the amplifier. at lower frequencies, flicker noise dominates, causing higher degrees of error for sub- hertz frequencies or dc precision applications. because the ad857x amplifiers are self-correcting op amps, they do not have increasing flicker noise at lower frequencies. in essence, low frequency noise is treated as a slowly varying offset error and is greatly reduced as a result of autocorrection. the correction becomes more effective as the noise frequency approaches dc, offsetting the tendency of the noise to increase exponentially as frequency decreases. this allows the ad857x to have lower noise near dc than standard low-noise amplifiers that are susceptible to 1/f noise. random autozero correction eliminates intermodulation distortion the ad857x can be used as a conventional op amp for gains up to 1 mhz. the autozero correction frequency of the device continuously varies, based on a pseudo-random generator with a uniform distribution from 2 khz to 4 khz. the randomization of the autocorrection clock creates a continuous randomization of intermodulation distortion (imd) products, which show up as simple broadband noise at the output of the amplifier. this noise naturally combines with the amplifiers voltage noise in a root-squared-sum fashion, resulting in an output free of imd. figure 50a shows the spectral output of an ad8572 with the amplifier configured for unity gain and the input grounded. figure 50b shows the spectral output with the amplifier configured for a gain of 60 db.
ad8571/ad8572/AD8574 C13C rev. 0 frequency C khz 0 2 160 0 10 1 output signal 23456789 2 20 2 40 2 60 2 80 2 100 2 120 v s = 5v a v = 0db 2 140 figure 50a. spectral analysis of ad857x output in unity gain configuration frequency C khz 0 0 10 1 output signal 23456789 2 20 2 40 2 60 2 80 2 100 v s = 5v a v = 60db 2 120 figure 50b. spectral analysis of ad857x output with 60 db gain figure 51 shows the spectral output of an ad8572 configured in a high gain (60 db) with a 1 mv input signal applied. note the absence of any imd products in the spectrum. the signal- to-noise (snr) ratio of the output signal is better than 60 db, or 0.1%. frequency C khz 0 0 10 1 output signal 23456789 2 20 2 40 2 60 2 80 2 100 v s = 5v a v = 60db 2 120 figure 51. spectral analysis of ad857x in high gain with an input signal broadband and external resistor noise considerations the total broadband noise output from any amplifier is primarily a function of three types of noise: input voltage noise from the amplifier, input current noise from the amplifier and johnson noise from the external resistors used around the amplifier. input voltage noise, or e n , is strictly a function of the amplifier used. the johnson noise from a resistor is a function of the resistance and the temperature. input current noise, or i n , creates an equiva- lent voltage noise proportional to the resistors used around the amplifier. these noise sources are not correlated with each other and their combined noise sums in a root-squared-sum fashion. the full equation is given as: e e ktr i r n total n s n s , =+ + () ? ? 2 2 1 2 4 (15) where, e n = the input voltage noise of the amplifier, i n = the input current noise of the amplifier, r s = source resistance connected to the noninverting terminal, k = boltzmanns constant (1.38 3 10 -23 j/k) t = ambient temperature in kelvin (k = 273.15 + c) the input voltage noise density, e n , of the ad857x is 51 nv/ ? hz , and the input noise, i n , is 2 fa/ ? hz . the e n , total will be domi- nated by input voltage noise provided the source resistance is less than 172 k w . with source resistance greater than 172 k w , the overall noise of the system will be dominated by the johnson noise of the resistor itself. because the input current noise of the ad857x is very small, i n does not become a dominant term unless r s is greater than 4 g w , which is an impractical value of source resistance. the total noise, e n, total , is expressed in volts-per-square-root hertz, and the equivalent rms noise over a certain bandwidth can be found as: ee bw n n total = , (16) where bw is the bandwidth of interest in hertz. for a complete treatise on circuit noise analysis, please refer to the 1995 linear design seminar book available from analog devices. output overdrive recovery the ad857x amplifiers have an excellent overdrive recovery of only 200 m s from either supply rail. this characteristic is particu- larly difficult for autocorrection amplifiers, as the nulling ampli- fier requires a substantial amount of time to error correct the main amplifier back to a valid output. figure 23 and figure 24 show the positive and negative overdrive recovery time for the ad857x. the output overdrive recovery for an autocorrection amplifier is defined as the time it takes for the output to correct to its final voltage from an overload state. it is measured by placing the amplifier in a high gain configuration with an input signal that forces the output voltage to the supply rail. the input voltage is then stepped down to the linear region of the amplifier, usually to half-way between the supplies. the time from the input signal step-down to the output settling to within 100 m v of its final value is the overdrive recovery time. most competitors auto- correction amplifiers require a number of autozero clock cycles to recover from output overdrive and some can take several milliseconds for the output to settle properly.
ad8571/ad8572/AD8574 C14C rev. 0 input overvoltage protection although the ad857x is a rail-to-rail input amplifier, care should be taken to ensure that the potential difference between the inputs does not exceed 5 v. under normal operating conditions, the amplifier will correct its output to ensure the two inputs are at the same voltage. however, if the device is configured as a com- parator, or is under some unusual operating condition, the input voltages may be forced to different potentials. this could cause excessive current to flow through internal diodes in the ad857x used to protect the input stage against overvoltage. if either input exceeds either supply rail by more than 0.3 v, large amounts of current will begin to flow through the esd protection diodes in the amplifier. these diodes are connected between the inputs and each supply rail to protect the input transistors against an electrostatic discharge event and are normally reverse-biased. however, if the input voltage exceeds the supply voltage, these esd diodes will become forward-biased. without current-limiting, excessive amounts of current could flow through these diodes causing permanent damage to the device. if inputs are subject to overvoltage, appropriate series resistors should be inserted to limit the diode current to less than 2 ma maximum. output phase reversal output phase reversal occurs in some amplifiers when the input common-mode voltage range is exceeded. as common-mode voltage is moved outside of the common-mode range, the outputs of these amplifiers will suddenly jump in the opposite direction to the supply rail. this is the result of the differential input pair shut- ting down, causing a radical shifting of internal voltages which results in the erratic output behavior. the ad857x amplifier has been carefully designed to prevent any output phase reversal, provided both inputs are maintained within the supply voltages. if one or both inputs could exceed either supply voltage, a resistor should be placed in series with the input to limit the current to less than 2 ma. this will ensure the output will not reverse its phase. capacitive load drive the ad857x has excellent capacitive load-driving capabilities and can safely drive up to 10 nf from a single 5 v supply. although the device is stable, capacitive loading will limit the bandwidth of the amplifier. capacitive loads will also increase the amount of overshoot and ringing at the output. an r-c snubber network, figure 52, can be used to compensate the amplifier against capacitive load ringing and overshoot. 5v r x 60 v v out v in 200mv p-p ad857x c l 4.7nf c x 0.47 m f figure 52. snubber network configuration for driving capacitive loads although the snubber will not recover the loss of amplifier band- width from the load capacitance, it will allow the amplifier to drive larger values of capacitance while maintaining a minimum of over- shoot and ringing. figure 53 shows the output of an ad857x driving a 1 nf capacitor with and without a snubber network. 10 m s 100mv with snubber without snubber v s = 5v c load = 4.7nf figure 53. overshoot and ringing are substantially reduced using a snubber network the optimum value for the resistor and capacitor is a function of the load capacitance and is best determined empirically since actual c load will include stray capacitances and may differ substantially from the nominal capacitive load. table i shows some snubber network values that can be used as starting points. table i. snubber network values for driving capacitive loads c load r x c x 1 nf 200 w 1 nf 4.7 nf 60 w 0.47 m f 10 nf 20 w 10 m f power-up behavior on power-up, the ad857x will settle to a valid output within 5 m s. figure 54a shows an oscilloscope photo of the output of the ampli- fier along with the power supply voltage, and figure 54b shows the test circuit. with the amplifier configured for unity gain, the device takes approximately 5 m s to settle to its final output voltage. this turn-on response time is much faster than most other autocorrection amplifiers, which can take hundreds of microseconds or longer for their output to settle. 5 m s 1v v out v+ 0v 0v bottom trace = 2v/div top trace = 1v/div figure 54a. ad857x output behavior on power-up
ad8571/ad8572/AD8574 C15C rev. 0 100k v ad857x 100k v v sy = 0v to 5v v out figure 54b. ad857x test circuit for turn-on time applications a 5 v precision strain-gage circuit the extremely low offset voltage of the ad8572 makes it an ideal amplifier for any application requiring accuracy with high gains, such as a weigh scale or strain-gage. figure 55 shows a configuration for a single supply, precision strain-gage measurement system. a ref192 provides a 2.5 v precision reference voltage for a2. the a2 amplifier boosts this voltage to provide a 4.0 v reference for the top of the strain-gage resistor bridge. q1 provides the cur- rent drive for the 350 w bridge network. a1 is used to amplify the output of the bridge with the full-scale output voltage equal to: 2 12 + () rr r b (17) where r b is the resistance of the load cell. using the values given in figure 55, the output voltage will linearly vary from 0 v with no strain to 4 v under full strain. v out 350 v load cell ad8572-a r 3 17.4k v r 4 100 v r 1 17.4k v r 2 100 v 0v to 4v note: use 0.1% tolerance resistors. 20k v a1 ad8572-b ref192 12k v 1k v 5v 2.5v 6 4 3 2 4.0v 40mv full-scale q1 2n2222 or equivalent a2 figure 55. a 5 v precision strain-gage amplifier 3 v instrumentation amplifier the high common-mode rejection, high open-loop gain, and operation down to 3 v of supply voltage makes the ad857x an excellent choice of op amp for discrete single supply instrumenta- tion amplifiers. the common-mode rejection ratio of the ad857x is greater than 120 db, but the cmrr of the system is also a function of the external resistor tolerances. the gain of the differ- ence amplifier shown in figure 56 is given as: vv r rr r r v r r out = + ? ? ? ? + ? ? ? ? - ? ? ? ? 112 4 34 1 2 2 1 (18) v2 v1 v out r 1 r 3 r 4 r 2 ad857x if r 3 r 4 = r 1 r 2 , then v out = r 1 r 2 3 (v1 2 v2) figure 56. using the ad857x as a difference amplifier in an ideal difference amplifier, the ratio of the resistors are set exactly equal to: a r r r r v == 2 1 4 3 (19) which sets the output voltage of the system to: vavv out v =- () 12 (20) due to finite component tolerance the ratio between the four resistors will not be exactly equal, and any mismatch results in a reduction of common-mode rejection from the system. referring to figure 56, the exact common-mode rejection ratio can be expressed as: cmrr rr rr rr rr r r = ++ - 14 24 23 14 23 2 22 (21) in the 3 op amp instrumentation amplifier configuration shown in figure 57, the output difference amplifier is set to unity gain with all four resistors equal in value. if the tolerance of the resis- tors used in the circuit is given as d , the worst-case cmrr of the instrumentation amplifier will be: cmrr min = 1 2 d (22) v out r r r r AD8574-c v2 r r v1 r g AD8574-b AD8574-a r trim v out = 1 + 2r r g (v1 2 v2) figure 57. a discrete instrumentation amplifier configuration thus, using 1% tolerance resistors would re sult in a worst-case system cmrr of 0.02, or 34 db. therefore either high precision resistors or an additional trimming resistor, as shown in figure 57, should be used to achieve high common-mode rejection. the value of this trimming resistor should be equal to the value of r multi- plied by its tolerance. for example, using 10 k w resistors with 1% tolerance would require a series trimming resistor equal to 100 w .
ad8571/ad8572/AD8574 C16C rev. 0 a high accuracy thermocouple amplifier figure 58 shows a k-type thermocouple amplifier configuration with cold-junction compensation. even from a 5 v supply, the ad8571 can provide enough accuracy to achi eve a resolution of better than 0.02 c from 0 c to 500 c. d1 is used as a tempera- ture measuring device to correct the cold-junction error from the thermocouple and should be placed as close as possible to the two term inating junctions. with the th ermocouple measuring tip immersed in a zero-degree ice bath, r 6 should be adjusted until the output is at 0 v. using the values shown in figure 58, the output voltage will track temperature at 10 mv/ c. for a wider range of tempera- ture measurement, r 9 can be decreased to 62 k w . this will create a 5 mv/ c change at the output, allowing measurements of up to 1000 c. ad8571 3 8 4 0v to 5v (0 8 c to 500 8 c) 5v 0.1 m f + 10 m f ref02ez 0.1 m f 12v 2 6 4 ++ CC d1 1n4148 5v k-type thermocouple 40.7 m v/ 8 c 1 r 6 200 v r 4 5.62k v r 9 124k v r 3 53.6 v r 5 40.2k v r 8 453 v r 1 10.7k v 2 r 2 2.74k v figure 58. a precision k-type thermocouple amplifier with cold-junction compensation precision current meter because of its low input bias current and superb offset voltage at single supply voltages, the ad857x is an excellent amplifier for precision current monitoring. its rail-to-rail input allows the amplifier to be used as either a high-side or low-side current monitor. using both amplifiers in the ad8572 provides a simple method to monitor both current supply and return paths for load or fault detection. figure 59 shows a high-side current monitor configuration. here, the input common-mode voltage of the amplifier will be at or near the positive supply voltage. the amplifiers rail-to-rail input provides a precise measurement, even with the input common-mode voltage at the supply voltage. the cmos input structure does not draw any input bias current, ensuring a minimum of measurement error. the 0.1 w resistor creates a voltage drop to the noninverting input of the ad857x. the amplifiers output is corrected until this voltage appears at the inverting input. this creates a current through r 1 , which in turn flows through r 2 . the monitor output is given by: monitor output r r r i sense l = ? ? ? ? 2 1 (23) using the components shown in figure 59, the monitor output transfer function is 2.5 v/a. figure 60 shows the low-side monitor equivalent. in this circuit, the input common-mode voltage to the ad8572 will be at or near ground. again, a 0.1 w resistor provides a voltage drop proportional to the return current. the output voltage is given as: vv r r ri out sense l =+- ? ? ? ? 2 1 (24) for the component values shown in figure 60, the output transfer function decreases from v at C2.5 v/a. 8 1 4 3 3v 0.1 m f r sense 0.1 v v+ i l g s d 2 m1 si9433 monitor output 3v 1/2 ad8572 r 1 100 v r 2 2.49k v figure 59. a high-side load current monitor v+ return to ground 1/2 ad8572 v+ v out q1 r 2 2.49k v r 1 100 v r sense 0.1 v figure 60. a low-side load current monitor precision voltage comparator the ad857x can be operated open-loop and used as a precision comparator. the ad857x has less than 50 m v of offset voltage when run in this configuration. the slight increase of offset voltage stems from the fact that the autocorrection architecture operates with lowest offset in a closed-loop configuration, that is, one with negative feedback. with 50 mv of overdrive, the device has a propagation delay of 15 m s on the rising edge and 8 m s on the falling edge. care should be taken to ensure the maximum differential volt- age of the device is not exceeded. for more information, please refer to the section on input overvoltage protection.
ad8571/ad8572/AD8574 C17C rev. 0 spice model the spice macro-model for the ad857x amplifier is given in listing 1. this model simulates the typical specifications for the ad857x, and it can be downloaded from the analog devices website at http://www.analog.com. the schematic of the macro-model is shown in figure 61. transistors m1 through m4 simulate the rail-to-rail input differ- ential pairs in the ad857x amplifier. the eos voltage source in series with the noninverting input establishes not only the 1 m v offset vo ltage, but is also used to establish common-mode and power supply rejection ratios and input voltage noise. the differ- ential voltages from nodes 14 to 16 and nodes 17 to 18 are reflected to e1, which is used to simulate a secondary pole-zero combination in the open-loop gain of the amplifier. the voltage at node 32 is then reflected to g1, which adds an additional gain stage and, in conjunction with cf, establishes the slew rate of the model at 0.5 v/ m s. m5 and m6 are in a common-source configuration, similar to the output stage of the ad857x amplifier. eg1 and eg2 fix the quiescent current in these two transistors at 100 m a, and also help accurately simulate the v out vs. i out characteristic of the amplifier. the network around ecm1 creates the common-mode voltage error, with ccm1 setting the corner frequency for the cmrr roll-off. the power supply rejection error is created by the network around eps1, with cps3 establishing the corner frequency for the psrr roll-off. the two current loops around nodes 80 and 81 are used to create a 51 nv/ ? hz noise figure across rn2. all three of these error sources are reflected to the input of the op amp model through eos. finally, gsy is used to accurately model the supply current versus supply voltage increase in the ad857x. this macro-model has been designed to accurately simulate a number of specifications exhibited by the ad857x amplifier, and is one of the most true-to-life macro-models available for any op amp. it is optimized for operation at 27 c. although the model will function at different temperatures, it may lose accuracy with respect to the actual behavior of the ad857x. 17 18 99 11 12 c2 r c7 r c8 r c3 r c4 d2 i2 v1 10 50 99 + 2 8 9 eos i1 d1 v1 2 r c2 r c1 c1 r c6 r c5 50 16 m2 m1 1 14 7 m3 m4 13 31 c2 r 2 32 r 3 + 2 e1 + eref 0 98 2 21 ccm1 r cm1 22 r cm2 ecm1 98 + 2 81 80 + 2 hn r n2 r n1 vn1 98 72 cps3 r ps3 73 r ps4 eps1 98 + 2 99 cps1 70 r ps1 0 r ps2 cps2 50 71 99 50 gsy m5 99 eg1 cf + d3 97 d4 + 2 evp evn 98 51 m6 r 1 98 g1 + 2 eg2 50 47 30 45 98 2 2 + 46 figure 61. schematic of the ad857x spice macro-model
ad8571/ad8572/AD8574 C18C rev. 0 spice macro-model for the ad857x * ad8572 spice macro-model * typical values * 7/99, ver. 1.0 * tam / adsc * * copyright 1999 by analog devices * * refer to readme.doc file for license * statement. use of this model indicates * your acceptance of the terms and * provisions in the license statement. * * node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * ||||| * ||||| .subckt ad8572 1 2 99 50 45 * * input stage * m1 4 7 8 8 pix l=1e-6 w=355.3e-6 m2 6 2 8 8 pix l=1e-6 w=355.3e-6 m3 11 7 10 10 nix l=1e-6 w=355.3e-6 m4 12 2 10 10 nix l=1e-6 w=355.3e-6 rc1 4 14 9e+3 rc2 6 16 9e+3 rc3 17 11 9e+3 rc4 18 12 9e+3 rc5 14 50 1e+3 rc6 16 50 1e+3 rc7 99 17 1e+3 rc8 99 18 1e+3 c1 14 16 30e-12 c2 17 18 30e-12 i1 99 8 100e-6 i2 10 50 100e-6 v1 99 9 0.3 v2 13 50 0.3 d1 8 9 dx d2 13 10 dx eos 7 1 poly(3) (22,98) (73,98) (81,98) + 1e-6 1 1 1 ios 1 2 2.5e-12 * * cmrr 120db, zero at 20hz * ecm1 21 98 poly(2) (1,98) (2,98) 0 .5 .5 rcm1 21 22 50e+6 ccm1 21 22 159e-12 rcm2 22 98 50 * * psrr=120db, zero at 1hz * rps1 70 0 1e+6 rps2 71 0 1e+6 cps1 99 70 1e-5 cps2 50 71 1e-5 epsy 98 72 poly(2) (70,0) (0,71) 0 1 1 rps3 72 73 15.9e+6 cps3 72 73 10e-9 rps4 73 98 16 * voltage noise reference of 51nv/rt(hz) * vn1 80 98 0 rn1 80 98 16.45e-3 hn 81 98 vn1 51 rn2 81 98 1 * * internal voltage reference * eref 98 0 poly(2) (99,0) (50,0) 0 .5 .5 gsy 99 50 (99,50) 48e-6 evp 97 98 (99,50) 0.5 evn 51 98 (50,99) 0.5 * * lhp zero at 7mhz, pole at 50mhz * e1 32 98 poly(2) (4,6) (11,12) 0 .5814 .5814 r2 32 33 3.7e+3 r3 33 98 22.74e+3 c3 32 33 1e-12 * * gain stage * g1 98 30 (33,98) 22.7e-6 r1 30 98 259.1e+6 cf 45 30 45.4e-12 d3 30 97 dx d4 51 30 dx * * output stage * m5 45 46 99 99 pox l=1e-6 w=1.111e-3 m6 45 47 50 50 nox l=1e-6 w=1.6e-3 eg1 99 46 poly(1) (98,30) 1.1936 1 eg2 47 50 poly(1) (30,98) 1.2324 1 * * models * .model pox pmos (level=2,kp=10e-6, + vto=-1,lambda=0.001,rd=8) .model nox nmos (level=2,kp=10e-6, + vto=1,lambda=0.001,rd=5) .model pix pmos (level=2,kp=100e-6, + vto=-1,lambda=0.01) .model nix nmos (level=2,kp=100e-6, + vto=1,lambda=0.01) .model dx d(is=1e-14,rs=5) .ends ad8572
ad8571/ad8572/AD8574 C19C rev. 0 outline dimensions dimensions shown in inches and (mm). 8-lead msop (rm suffix) 85 4 1 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) pin 1 0.0256 (0.65) bsc 0.122 (3.10) 0.114 (2.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33 8 27 8 0.120 (3.05) 0.112 (2.84) 8-lead soic (r suffix) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 8-lead tssop (ru suffix) 8 5 4 1 0.122 (3.10) 0.114 (2.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.0256 (0.65) bsc seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 8 0 8 14-lead tssop (ru suffix) 14 8 7 1 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 8 0 8 14-lead soic (r suffix) 14 8 7 1 0.3444 (8.75) 0.3367 (8.55) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 8 0 8 0.0196 (0.50) 0.0099 (0.25) x 45 8 c3734C2.5C10/99 printed in u.s.a.

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